Empirical multichannel power consumption model for erbium-doped fiber amplifiers

In this paper we report on the first experimental power consumption analysis and model of single and multi-stage booster erbium-doped fiber amplifiers (EDFAs) with automatic gain control (AGC), accounting for channel number dependency. Results show that the amount of channels being amplified simultaneously contributes significantly, up to 48%, to the total power consumption due to the circuitry used for controlling the EDFA. As the number of simultaneous amplified WDM channels in high capacity long and medium reach transmission links reflects closely traffic patterns generated by end-users, it is relevant to study channel number dependent power consumption for devising EDFA power efficient control and design

Free-running L-band VCSEL for 1.25 Gbps hybrid radio-fiber cloud optical interconnects

International audienceWe demonstrate a free-running directly-modulated 1580 nm VCSEL suitable for hybrid wireless/optical interconnects supporting cloud data centers. Error-free transmission at 1.25 Gbps was achieved after 6.5 GHz wireless link and 1 km bend-insensitive fiber

Digital Signal Processing for a Sliceable Transceiver for Optical Access Networks

Methods to upgrade the network infrastructure to cope with current traffic demands has attracted increasing research efforts. A promising alternative is signal slicing. Signal slicing aims at re-using low bandwidth equipment to satisfy high bandwidth traffic demands. This technique has been used also for implementing full signal path symmetry in real-time oscilloscopes to provide performance and signal fidelity (i.e. lower noise and jitter). In this paper the key digital signal processing (DSP) subsystems required to achieve signal slicing are surveyed. It also presents, for the first time, a comprehensive DSP power consumption analysis for both WDM and TDM systems at 1 Gbps and 10 Gbps, discussing latency penalties for each approach. For 1 Gbps WDM system 278 pJ per information bit for 4 slices is reported at 105 ns latency penalties, whereas 3898.4 pJ per information bit at 183.5 µs latency penalty is reported for 10 Gbps. Power savings of the order of hundreds of Watts can be obtained when using signal slicing as an alternative to 10 Gbps implemented access networks. Methods to upgrade the network infrastructure to cope with current traffic demands has attracted increasing research efforts. A promising alternative is signal slicing. Signal slicing aims at re-using low bandwidth equipment to satisfy high bandwidth traffic demands. This technique has been used also for implementing full signal path symmetry in real-time oscilloscopes to provide performance and signal fidelity (i.e. lower noise and jitter). In this paper the key digital signal processing (DSP) subsystems required to achieve signal slicing are surveyed. It also presents, for the first time, a comprehensive DSP power consumption analysis for both WDM and TDM systems at 1 Gbps and 10 Gbps, discussing latency penalties for each approach. For 1 Gbps WDM system 278 pJ per information bit for 4 slices is reported at 105 ns latency penalties, whereas 3898.4 pJ per information bit at 183.5 μs latency penalty is reported for 10 Gbps. Power savings of the order of hundreds of Watts can be obtained when using signal slicing as an alternative to 10 Gbps implemented access networks

Power-Aware Multi-Layer Translucent Network Design: an Integrated OPEX/CAPEX Analysis

We propose a three-phase network design model minimizing CAPEX and OPEX in IP-over-WDM architectures. By forbidding reconfiguration (accounting for 58\% of the OPEX) we achieve only 4.2\% increase in power consumption at no CAPEX expenses. We propose a three-phase network design model minimizing CAPEX and OPEX in IP-over-WDM architectures. By forbidding reconfiguration (accounting for 58% of the OPEX) we achieve only 4.2% increase in power consumption at no CAPEX expenses